The present invention relates to a pulse width modulation (hereinbelow abbreviated xe2x80x9cPWMxe2x80x9d) pulse control method in a power converter such as an inverter that implements system interconnection or variable-speed drive of a motor that is load, and more particularly to a PWM pulse control method for realizing lower noise of an inverter that performs three-phase drive.
We refer first to FIG. 1, which is a circuit diagram showing the configuration of a three-phase two-level PWM inverter. As shown in FIG. 1, a three-phase two-level PWM inverter is composed of dc power supply 101, capacitor 102, U-phase, V-phase, and W-phase output terminals 117-119 of a motor, semiconductor switching elements (for example, IGBT and GTO) 103-108, and diodes 109-114.
When semiconductor switching elements 103, 105, and 107 are turned ON, output terminals 117-119 for each phase are connected to positive bus 115, which leads from the positive electrode of the dc power supply, and the output phase voltage of each phase becomes a high level (hereinbelow abbreviated xe2x80x9cHxe2x80x9d). When semiconductor switching elements 104, 106, and 108 are turned ON, output terminals 117-119 for each phase are connected to negative bus 116, which leads from the negative electrode of the dc power supply, and the output phase voltage of each phase becomes a low level (hereinbelow abbreviated xe2x80x9cLxe2x80x9d).
Modulation methods for such a three-phase two-level PWM inverter include a three-phase modulation method and a two-phase modulation method. The three-phase modulation method realizes modulation by varying the voltage levels of all three phases. The two-phase modulation method realizes modulation by fixing the output phase voltage of one of the three phases to the high level (H) or low level (L) and then modulating the remaining two phases. In the two-phase modulation method, the fixed phase is switched by the phase of the output phase voltage.
In such a three-phase two-level PWM inverter, the two-phase modulation method is generally used when the modulation percentage and output frequency of the inverter are both high, and the three-phase modulation method is generally used when the modulation percentage and output frequency are low.
Since pulses of three phases are output at the same time in the three-phase modulation method, the width of PWM pulses can be made longer than in the two-phase modulation method. When the modulation percentage and the output frequency of the inverter are both low, the time interval in which the output voltage vector is a zero vector increases and the width of the PWM pulses of each phase therefore decreases.
Since the switching of the semiconductor switching elements cannot be followed when the width of the PWM pulses becomes too small, the three-phase modulation method, in which the PWM pulse width is greater, is employed when the output frequency of the inverter is low.
As for the prior-art PWM pulse control method of a PWM inverter in which the three-phase modulation method is employed, the phase state when output terminals 117-119 for each phase are connected to positive bus 115 is referred to as the first state (hereinbelow abbreviated xe2x80x9cPxe2x80x9d), and the phase state when output terminals 117-119 are connected to negative bus 116 is referred to as the second state (hereinbelow abbreviated xe2x80x9cNxe2x80x9d). Further, when the output states of the three phases in the order of U-phase, V-phase, and W-phase is (P, P, P), the output voltage vector is the Op-vector, and when the output states of the three phases is (N, N, N), the output voltage vector is the On-vector. The output voltage vector is the a-vector when the output states are (P, N, N), (N, P, N), and (N, N, P); and the output voltage vector is the b-vector when the output states are (P, P, N), (N, P, P), and (P, N, P). The a-vector is the output voltage vector when any one phase of the three phases is P, and the b-vector is the output voltage vector when any one phase of the three phases is N.
We now refer to FIG. 2, which is a timing chart showing the PWM pulse control method of the prior art. Triangular wave voltage 4 is the PWM carrier signal of the PWM inverter. Voltage commands 5-7 indicate voltage commands of the W-phase, the V-phase, and the U-phase, respectively. PWM pulse 1 of the U-phase, PWM pulse 2 of the V-phase, and PWM pulse 3 of the W-phase are shown beneath the signal and commands. The output terminals of each phase are connected to positive bus 115 and the output state of each phase is P when PWM pulses 1-3 are H; and the output terminals of each phase are connected to negative bus 116 and the output states of each phase is N when PWM pulses 1-3 are L. Since the cycle of voltage commands 5-7 is extremely long, the values of voltage commands 5-7 show virtually no fluctuation within a single cycle of triangular-wave voltage 4.
In the PWM pulse control method of the prior art, PWM pulses 1-3 are each L when the value of triangular wave voltage 4 exceeds the value of each of the respective voltage commands 5-7, and PWM pulses 1-3 are each H when the value of triangular wave voltage 4 falls below each of the respective values of voltage commands 5-7. In this case, the output voltage vectors undergo transitions within one cycle of triangular wave voltage 4 in the order: Op-vector-b-vector-a-vector-On-vector-a-vector-b-vector-Op-vector.
We next refer to FIG. 3, which is a circuit diagram showing the constitution of a three-phase three-level PWM inverter. As shown in FIG. 3, a three-phase three-level PWM inverter is made up by: dc power supply 201; capacitors 202 and 203; U-phase, V-phase, and W-phase output terminals 117-119 of a motor; neutral point 252, semiconductor switching elements 230-241, and diodes 204-221.
When semiconductor switching elements 230 and 231, 234 and 235, and 238 and 239 are turned ON, output terminals 117-119 of each phase are connected to positive bus 250 and the output phase voltage of each phase becomes H. When semiconductor switching elements 231 and 232, 235 and 236, and 239 and 240 are turned ON, output terminals 117-119 of each phase are connected to neutral point 252 and the output phase voltage of each phase becomes an intermediate level between H and L (hereinbelow abbreviated xe2x80x9cMxe2x80x9d). When semiconductor switching elements 232 and 233, 236 and 237, and 240 and 241 are turned ON, output terminals 117-119 of each phase are connected to negative bus 251 and the output phase voltage of each phase becomes L.
The three-phase three-level PWM inverter modulation method described in the foregoing explanation includes unipolar modulation and dipolar modulation. Unipolar modulation is a mode in which PWM pulses are output in which the output level of the output phase voltage is repeatedly H and M when the voltage command value is a positive value, and PWM pulses are output in which the output level of the output phase voltage is repeatedly M and L when the voltage command value is a negative value. Dipolar modulation is a mode in which a PWM pulse is output in which the output level of the output phase voltage repeatedly alternates between H and L on either side of M within one cycle of the PWM carrier signal regardless of whether the voltage command value is negative or positive.
In such a three-phase three-level PWM inverter, unipolar modulation is generally used when the output frequency and modulation percentage are both high, and dipolar modulation is generally employed when output frequency and modulation percentage are both low. This is because one side of the semiconductor switching elements repeatedly switch between ON and OFF over a long time period if unipolar modulation is used when the output frequency is low, raising the danger of breakdown of these semiconductor switching elements.
Explanation next regards the prior-art PWM pulse control method for a PWM inverter in which dipolar modulation is employed. The state of each phase when output terminals 117-119 of each phase are connected to positive bus 250 is P, the state of each phase when output terminals 117-119 of each phase are connected to negative bus 251 is N, and the state of each phase when output terminals 117-119 of each phase are connected to neutral point 252 is a third sate (hereinbelow referred to as xe2x80x9cOxe2x80x9d).
Further, the output voltage vector is the Op-vector when the output state of the three phases in the order of U-phase, V-phase, and W-phase is (P, P, P); the output voltage vector is the On-vector when the output state is (N, N, N); and the output voltage vector is the Oo-vector when the output state is (O, O, O). The output voltage vector is the ap-vector when the output state is (P, O, O), (O, P, O), or (O, O, P); the output voltage vector is the an-vector when the output state is (O, N, N), ((N, O, N) or (N, N, O); the output voltage vector is the bp-vector when the output state is (P, P, O), (O, P, P), or (P, O, P); and the output voltage vector is the bn-vector when the output state is (O, O, N), (N, O, O) or (O, N, O).
FIG. 4 is a timing chart showing the dipolar modulation PWM pulse control method of the prior art. This chart shows the output state of each phase of a three-phase motor within one cycle Tc of triangular voltage 4, which is the voltage of the PWM carrier signal. Voltage commands 5-7 represent the voltage commands of the W-phase, V-phase and U-phase, respectively.
FIG. 4 shows PWM pulses of each phase 1-3 in the prior art in one cycle of triangular wave voltage 4 of the prior-art PWM pulse control method. As shown in FIG. 4, within one cycle of triangular wave voltage 4, the output voltage vector undergoes transitions in the order: Op-vector-bp-vector-ap-vector-Oo-vector-bn-vector-an-vector-On-vector; or in the opposite order.
In the above-described PWM inverter, current flows to specific semiconductor switching elements over a long period when the output frequency is extremely low, and a method has therefore been proposed by which the cycle of the PWM carrier signal is lengthened to reduce the number of instances of switching and thus decrease switching loss. However, lowering the frequency of the PWM carrier signal also lowers the frequency of the ripple component of current that flows to the motor, and this results in the problem that, of the frequency components of sound that is produced by the ripple component of the current, frequency components that are within the spectrum of human hearing are increased.
As described above, when the output frequency is low in a PWM inverter of the prior art, the frequency of the PWM carrier signal is set low, whereby the instances of switching by semiconductor switching elements are decreased to reduce the switching loss and prevent breakdown of semiconductor switching elements. However, lowering the frequency of the PWM carrier signal raises the problem that the frequency of the ripple component of the current that flows to the motor is also lowered, whereby, of the frequency components of sound that is produced by the ripple component of the current, the frequency component that is within the spectrum of human hearing is increased.
It is an object of the present invention to provide a PWM pulse control method in which, of the frequency components of sound that is produced by current ripple, the frequency component that is within the spectrum of human hearing is not increased even when the frequency of a PWM carrier signal is set to a low level.
To achieve the above-described object in the PWM pulse control method of the present invention, when the output frequency of a three-phase two-level inverter is set low and the frequency of a PWM carrier signal is also set low, PWM pulses are generated in which the output times of the output voltage vectors of each phase are divided by a first set value and a second set value. Adopting this method enables the frequency of current ripple, which is a ripple component that is caused by PWM pulses that are contained in the current that flows to the load, to differ for each phase, whereby the frequency component of the current ripple that is caused by PWM pulses can be dispersed. As a result, of the frequency components of sound that is produced by current ripple, the frequency component that is within the spectrum of human hearing can be prevented from reaching a high level.
In an embodiment of the PWM pulse control method of the present invention, when the PWM pulses are too short and the switching of semiconductor switching elements cannot be performed effectively because the divided times resulting from the first set value and second set value are short, a smaller value is set by the first set value and the second set value to decrease the number of divisions of each vector. The divided times can thus be lengthened and switching of the semiconductor switching elements can therefore be performed smoothly.
In an embodiment of the PWM pulse control method of the present invention, the entire ON-delay correction amount of PWM pulses is an ON-delay correction amount that is calculated based on the first set value and second set value that are determined when seeking the divided times of each vector and is the sum of a first ON-delay correction amount and second ON-delay correction amount. Adopting this form enables ON-delay correction of PWM pulses that is free of overcompensation and that accords with the number of instances of switching of semiconductor switching elements of an actual inverter, and therefore enables correction, without overcorrection or undercorrection, of distortion that arises from ON-delay in the output current of an inverter.
Further, in an embodiment of the PWM pulse control method of the present invention, PWM pulses are divided based on a PWM pulse to which has been added a first ON-delay correction amount for which the first set value and second set value are calculated as 1. Adopting this form enables division of PWM pulses using a PWM pulse that is close to the PWM pulses that are actually output to an inverter.
In an embodiment of the PWM pulse control method of the present invention, the cycle of the PWM carrier signal is lengthened with increase in the first and second set values. Adopting this form can prevent the PWM pulse width from becoming shorter than necessary, and as a result, switching of semiconductor switching elements can be carried out smoothly.
In another PWM pulse control method of the present invention, when the output frequency of a three-phase neutral-point clamping inverter and the frequency of the PWM carrier signal are both set to low levels, the output times of the output voltage vectors of each phase are divided by first, second, third, and fourth set values and PWM pulses then generated. By adopting this form, the frequency of current ripple, which is a ripple component arising from PWM pulses that are contained in current that flows to a load, differs for each phase and the frequency components of current ripple that arises from PWM pulses can be dispersed, whereby, of the frequency components of sound that is produced by current ripple, frequency component within the spectrum of human hearing can be prevented from reaching a high level.
In an embodiment of the PWM pulse control method of the present invention, when PWM pulses become too short due to the shortness of divided times resulting from the first, second, third, and fourth set values and switching of semiconductor switching elements cannot be performed effectively, a small value is set by means of the first, second, third, and fourth set values to decrease the number of divisions of each vector. Adopting this method enables lengthening of the divided times of each vector, whereby switching of the semiconductor switching elements can be performed smoothly.
In an embodiment of the PWM pulse control method of the present invention, the entire ON-delay correction amount of PWM pulses is an ON-delay correction amount that is calculated based on the first, second, third, and fourth set values that are determined when finding the divided times of each vector and is the sum of a first and a second ON-delay correction amounts. Adopting this form enables ON-delay correction of PWM pulses without overcompensation or undercompensation in accordance with the number of instances of switching of semiconductor switching elements of an actual inverter. As a result, the PWM pulse control method of the present invention enables correction without excess or deficiency of distortion of the output current of an inverter that is caused by ON-delay.
In an embodiment of the PWM pulse control method of the present invention, PWM pulses are divided based on a PWM pulse to which has been added a first ON-delay correction amount that is calculated with the first set value and second set value as 1. Adopting this form enables division of PWM pulses using PWM pulses that are close to the PWM pulses that are actually output to an inverter.
Finally, in an embodiment of a PWM pulse control method of the present invention, the cycle of the PWM carrier signal is made longer than the current cycle with increase in the first, second, third, and fourth set values. Adopting this form can prevent the PWM pulse width from becoming shorter than is necessary, whereby switching of semiconductor switching elements can be performed smoothly.